Modbus® RTU protocol – Hydramotion

The VP550 supports a single RS485 (multidrop) serial port. The communication follows the Modbus®protocol‡, varied to allow single precision floating-point numbers to be represented in two consecutive registers as eight hexadecimal digits. The VP550 acts as a slave to a host computer. Up to 16 slaves, each identified by a unique address, may be connected on the same RS485 serial line.

A3.1 Serial settings

The host computer is responsible for initiating all communications. The host computer should not poll more than once per second.
The VP550 will normally adopt the correct protocol automatically. If necessary, however, the protocol can be set by navigating to SETUP > VP SETUP > SERIAL SETTINGS > Mode.
The VP550 settings must match those of the slave viscometer.
Communication parameters are set as follows:

baud rate	9600
parity	EVEN
slave address	range 1 - 16 (decimal) (≡ 0001 - 0010 hexadecimal)

The default slave address is 1. To view or modify the address, navigate to SETUP > VP SETUP > SERIAL SETTINGS > ADDR.

A3.1.1 Byte format

Required:
EVEN parity
8 data bits §
1 stop bit
With the exception of the end frame (see below), all characters are in the ASCII range 20* - FF*. See table left for a selection of ASCII codes.

A3.1.2 Message framing

In a Modbus® RTU (“Remote Terminal Unit”) message, two 4-bit hexadecimal characters are packed into one byte. In ASCII mode, one byte contains only one hexadecimal character. For example, the value C9 (hex) is sent as one 8-bit byte (11001001) in RTU mode but as two bytes (00001100 “C” and 0001001 “9”) in ASCII mode.
Unlike ASCII messages, an RTU message does not include specific start or end characters. Messages must be separated by intervals of at least 3.5 character times (any shorter interval will set an error). A message starts with the 8-bit slave address and ends with a 16-bit Cyclic Redundancy Check (CRC).
The CRC method is as follows:
(1) A 16-bit register is loaded with FFFF (hex) (= binary 1111111111111111). This register is referred to as the “CRC Register”.
(2) The first 8-bit byte of the message is XORed (exclusive ORed) with the low-order byte of the CRC Register (any start, stop and/or parity bits are ignored). The result is placed in the CRC Register.
(3) The CRC Register is shifted one bit to the right, i.e. one bit towards the least significant bit (“LSB”). The most significant bit (“MSB”) is filled with a 0 (zero).
(4) The LSB is extracted and examined:
(i) if LSB = 0, step (3) above is repeated;
(ii) if LSB = 1, the CRC Register is XORed with A001 hex (= binary 1010000000000001)
and the result placed in the CRC Register.
(5) Steps (3) and (4) are repeated until 8 shifts have been performed, i.e. until the byte has been completely processed.
(6) Steps (2) to (5) are repeated for the next 8-bit byte, and so on until all 8-bit bytes have been processed. The final contents of the CRC Register is the CRC value.
When the CRC is transmitted, the low-order byte is sent first.
All data addresses are referenced to zero, so registers 1 - 16 are addressed as 0000 - 000F (hexadecimal).
The VP550 supports both unsigned 16-bit scaled integers (recommended) and single-precision floating-point numbers. The corresponding data addresses are given in Sections A3.2.1 and A3.3.2 below.
The VP550 tests the high-order digit of the requested data address to determine the format of the response message. So for example, if the data address is 0000 the VP550 reply will represent the data registers in 16-bit scaled integer format, while if the data address is 1000 the reply will represent the data registers in floating-point format.
The maximum register count is 16 for 16-bit scaled integers and 8 for floating-point data.

A3.2 16-bit scaled integers

A3.2.1 Data address map

Input registers for unsigned 16-bit scaled integers are mapped as follows:

*Alarms are mapped into a floating-point register, but must be decoded as a converted integer where

bit:

0 = instrument restarted
1 = e² fail
2 = frequency (2) fail 3 = frequency (3) fail
4 = PRT read fail
5 = PRT data error
6 = CALCULATION fail

A2.2.2 Scaling factors

For 16-bit scaled integers, the VP550 scales the registers using user-definable or preset scaling factors. Input register scaling factors are:

Note: The above viscosity and temperature scales are factory default values. These will be overridden by the corresponding user-defined 4-20mA output limits (Section 3.3.6).

The contents of a register are calculated using the formula

where P is the actual value of the selected parameter.

For example:
If averaged live viscosity (VL) = 200 cP, viscosity lo scale (4 mA) is set to 0 and
hi scale (20 mA) is set to 1000:

The maximum number of registers that can be requested in this format is 16.

A3.3 Floating-point numbers

A3.3.1 Format of floating-point numbers

• Any number n can be represented as a “floating-point number” by analysing it into a base number (also called “radix”) b, an exponent e and a mantissa m, such that
n = b^e × m,
• A binary floating-point number has b = 2. Then for example, the floating-point representation of 16 would be
16 = 2⁴ × 1.0

The Institute of Electrical and Electronics Engineers (IEEE) has produced a standard for floating-point arithmetic. This standard specifies how single-precision (32-bit) and double-precision (64-bit) binary floating-point numbers are to be represented, as well as how arithmetic should be carried out on them. The full title of the standard is IEEE Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Std 754-1985), also known as IEC 60559:1989, Binary floating-point arithmetic for microprocessor systems.
The VP550 uses single-precision (32-bit) floating-point numbers.
The IEEE single-precision floating-point standard representation requires a 32-bit word. The first bit is the sign bit, S, the next eight bits are the exponent bits, E, and the final 23 bits are the mantissa M:
Note that the least significant bits are to the left. S is 0 if the number is positive, 1 if it is negative.
The exponent is biased by 2⁽⁸⁻¹⁾ − 1 = 2⁷ − 1 = 127. Biasing is done because exponents have to be signed values in order to be able to represent both tiny and huge values, but two’s complement, the usual representation for signed values, would make comparison harder. To solve this the exponent is biased before being stored, by adjusting its value to put it within an unsigned range suitable for comparison.
The most significant bit of the mantissa is determined by the value of exponent. If 0 < exponent < 127, the most significant bit of the mantissa is 1, and the number is said to be “normalized”. If the exponent is 0, the most significant bit of the mantissa is 0 and the number is said to be “denormalised” or “unnormalised”. Three special cases arise:
(1) if exponent is 0 and mantissa is 0, the number is ±0 (depending on the sign bit),
(2) if exponent = 127 and mantissa is 0, the number is ± ∞ (again depending on the sign bit), and
(3) if exponent = 127 and mantissa is not 0, the entity being represented is not a number (“NaN”).

I.e.
0 00000000 00000000000000000000000 = 0
1 00000000 00000000000000000000000 = –0

0 11111111 00000000000000000000000 = ∞
1 11111111 00000000000000000000000 = – ∞

0 11111111 00000100000000000000000 = NaN
1 11111111 00100010001001010101010 = NaN

Example

To encode the decimal number −118.625 using the IEEE 754 system:
(1) Because it is a negative number, the sign S is 1.
(2) Write the number (without the sign) using binary notation. The result is 1110110.101.
(3) Move the point leftwards until there is only one digit to its left: 1110110.101 = 1.110110101 × 2⁶. This is a normalised floating-point number.
(4) The mantissa is the part to the right of the point. This must be filled with trailing 0s to the right to make it up to 23 bits, giving 11011010100000000000000.
(5) The exponent is 6. The bias is 127, so the exponent becomes 6 + 127 = 133. In binary, this is written as 10000101.

A2.3.2 Data address map (floating-point numbers)

Input registers for single-precision floating point numbers are mapped as follows:

*Alarms are mapped into a floating-point register, but must be decoded as a converted integer where bit
0 = instrument restarted
1 = e² fail
2 = frequency (2) fail
3 = frequency (3) fail
4 = PRT read fail
5 = PRT data error
6 = CALCULATION fail

The maximum number of registers that can be requested in this format is 8.

A3.4 Query-response overview

A3.4.1 Query-response format

The general format for a message issued by the host computer (where N = number of characters transmitted, B = number of bits) is:

The general format for the VP550 response is:

• The VP550 uses function codes 3 and 4 only.

A3.4.2 Examples of query-response messages

(1) Unsigned 16-bit scaled integer format
Request to read four input registers (function code 04) from slave address 01, starting at data address 0000:
(i) bytes

1a. Poll (Tx)
01 04 00 00 00 04 F1 C9

1b. Response (Rx)
01 04 08 2F B9 27 6F 2F BA 27 70 AF 65

(iii) analysis

1a. Tx
:010400000004F7

1b. Rx
:01040800790079007B007B0B

In this example, actual values are:

VL (“live” viscosity): 186.42
4 mA (lo scale): 0
20 mA (hi scale): 1000

hence